1. Field of the Art
This document relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode display device which has a structure devised to overcome defects that might occur during the process of simplifying the manufacture of the organic light emitting diode display device.
2. Discussion of the Related Art
In recent years, various types of flat panel displays having reduced weight and volume, which are drawbacks of cathode ray tubes (CTRs), have been developed. These flat panel displays comprise liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and electroluminescence devices (ELs).
FIG. 1 is a top plan view showing the structure of an organic light emitting diode display device (OLED) using a thin film transistor (TFT) as an active element according to the prior art. FIG. 2 is an enlarged view of area A of FIG. 1. FIG. 3 is a cross-sectional view showing the structure of the organic light emitting diode display device according to the prior art taken along the line I-I′ of FIG. 2. FIG. 4 is a photograph showing coating blotches on a bank layer.
Referring to FIGS. 1 to 3, the organic light emitting diode display device comprises an active area 10 where an image is displayed on a substrate 100 and a driver 20 for applying driving signals to the active area 10. More specifically, the organic light emitting diode display device comprises a driving thin film transistor (hereinafter, referred to as ‘driving TFT’) 40, an organic light emitting diode 60 driven in connection with the driving TFT 40, and a sealing member (not shown) for sealing the substrate 100. The substrate 100 comprises a switching thin film transistor (hereinafter, referred to as ‘switching TFT) 30, the driving TFT 40, a capacitor 50 connected to the driving TFT 40, and an organic light emitting diode connected to the driving TFT 40.
To manufacture the organic light emitting diode display device, a buffer layer 105 is formed on a glass substrate 100, and a switching TFT 30 is formed at a crossing portion of a gate line 35 and a data line 37. The switching TFT 30 comprises a gate electrode 120S branched from the gate line 35, a semiconductor layer (not shown), a source electrode 130S, and a drain electrode 130D. The driving TFT 40 comprises a gate electrode 120D connected to the drain electrode 130D of the switching TFT 30, a semiconductor layer 110D, a source electrode 132S connected to a driving current line 39, and a drain electrode 132D. The drain electrode 132D of the driving TFT 40 is connected to an anode 150 of the organic light emitting diode 60.
The semiconductor layer 110D of the driving TFT 40 and a capacitor lower electrode 110C are formed on the substrate 100. On a gate insulating film 115 overlying the semiconductor layer 110D and the capacitor lower electrode 110C, the gate electrode 120D is formed to overlap the center of the semiconductor layer 110D and a capacitor intermediate electrode 120C is formed to overlap the capacitor lower electrode 110C. The source electrode 132S and the drain electrode 132D are connected to both sides of the semiconductor layer 110D through contact holes. The source electrode 132S and the drain electrode 132D are formed on an interlayer insulating film 125 covering the gate electrode 120D, and the source electrode 132S is connected to a capacitor upper electrode 132C.
A ground line 70 to be connected to a cathode (not shown) of the organic light emitting diode 60 is formed on the outer periphery of the active area 10. The ground line 70 has a gate ground line 120G formed on the gate insulating film 115 and a source ground line 134G formed on the interlayer insulating film 125 and connected to the gate ground line 120G. A planarization film 140 is applied on a display region of the substrate 100. The planarization film 140 is patterned to form contact holes that expose the drain electrode 132D of the driving TFT 40. The anode 150 is formed on the planarization film 140 to come into contact with the drain electrode 132D of the driving TFT 40 through a contact hole.
A bank layer 160 is formed across the entirety of the substrate 100 everywhere except in a light emitting region. This means that during this stage of the manufacturing process, the bank layer 160 is initially deposited on top of the ground line 70. The bank layer 160 is then patterned by removing portions of the initially deposited bank layer 160 (not shown in FIG. 3). Subsequent to the patterning of the bank layer, a light emitting layer (not shown) is formed on the anode 150, and a cathode (not shown) is then formed to cover the remaining portion of the bank layer on top of the light emitting layer 155.
However, a problem arises from depositing and then removing/patterning the bank layer 160 in this way. Removal of all of a given section of the bank layer 160 is not always a completely successful process, and often some amount of bank layer 160 will remain after removal. For example during the removal, any bank layer 160 that was initially present on top of the ground line 70 is ideally removed during the bank removal/patterning process. However, often some amount of bank layer 160 will be left over on the surface of the ground line 70.
Often, the material used to make the bank layer 160, for example polyimide, has poor interface characteristics with metal layer made out of molybdenum-titanium (MoTi) or copper (Cu), an example of which is ground line 70. Poor interface characteristics include the inability to form a strong bond with adjacent materials. For example, polyamide cannot strongly bond with MoTi or Cu. As a result, when the bank layer 160 is initially formed and then removed from the ground line 70, leftover bank layer that was not able to be removed during the removal process will result in poor interface characteristics between the ground line 70 and whatever layer is later formed on the ground line 70. For example, if the cathode (not shown) is later formed on the ground line 70, intervening leftover bank layer can result in a poor interface with the cathode. FIG. 4 illustrates an example of incomplete bank layer removal. The leftover bank layer appears in FIG. 4 as irregularities in the thickness of the bank layer or as blotches.
Consequently, the leftover bank layer in between the ground line 70 and the cathode can result in a poor bond between these two layers. As a result, the two layers may separate over time, and create a path for moisture to penetrate into the display region of the device. Over time, this may negatively affect the performance of the organic light emitting diode display device. The leftover bank layer may also create visible blotches in the display region, which is highly undesirable.